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  Location: Home > Faculty
Name:  
  LIU Hongyue  刘虹越
Department:  
  Division of Interdisciplinary Research
Position:  
  Professor
Expertise:  
  Semiconductor memory design; Mixed-signal circuit design; Optimization of storage systems engineering; Technology integration; Semiconductor device physics
Email:  
  hyliu2010@sinano.ac.cn

Research Interest:

1. Development of core FTL algorithms in solid state storage controller;

2. Development of PCIe based solid state drive with high I/O speed and large capacity;

3. Management of solid state drives in tiered storage system;

4. Mechanism of using solid state storage as cache in High Performance Computing. 

 
Experience:
Employment

Jan. 2012 - Present

Professor

Division of Interdisciplinary Research, SINANO, CAS

Apr. 2010 – Dec. 2011

Professor

Division of Nanodevices & Materials, SINANO, CAS

Jan. 2007 - Mar. 2010

Senior Director

Seagate 

Mar. 2003 - Jun. 1999

Senior Device Engineer

Honeywell

Education

Ph.D. 1996 

Materials 

The Pennsylvania State University

B.S. 1991

Applied Physics

Tsinghua University

 
Selected Publication:
  1. Liu Hongyue, "STRAM for Embedded and Stand-alone Applications”, Invited Presentation, Spring MRS Conference in San Francisco, 2009
  2. Liu Hongyue, "Tomorrow for Magnetism”, Invited Presentation, The International Symposium on Low Power Electronics and Design (ISLPED), 2007
  3. Y. Chen, X. Wang, H. Li, H. Liu, D. Dimitrov, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)“,  the ISQED 2008 best paper
  4. X. Wang, Y. Chen, H. Li, D. Dimitrov, H. Liu, "Spin Torque Random Access Memory Down to 22nm Technology”, Magnetics IEEE Trans., Vol. 44, Issue 11, Part 1, Nov. 2008, Pages 2479-2482
  5. S.T. Liu, A. Hurst, H. Liu, H. Hughes, M. Mendicino, R. Reed, "SEU Cross-sections of 6T SOI CMOS SRAMs”,   2008 IEEE SOI International Conference Proceedings, Pages 131-132
  6. S.T. Liu, D. Nelson, J. Tsang, K. Golke, P. Fechner, W. Heikkila, N. Brewster, R. Van Cleave, H. Liu, P. McMarr, H. Hughes, J. Ziegler, "The Effect of Active Delay Element Resistance on Limiting Heavy Ion SEU Upset Cross-sections of SOI ADE/SRAMs”,  IEEE Trans. Nucl. Sci., Vol. 54, Issue 6, Part1, Dec. 2007, pages  2480-2487
  7. H. Liu, S.T. Liu and H. Hughes, "Proton Induced SEU Single Event Upset in 6T SRAMs”,  IEEE Trans. Nucl. Sci., Vol. 53, Issue 6, Part1, Dec. 2006, pages  3502-3505
  8. "A New Mechanism of Heavy Ion Induced Upset in SOI SRAMs”, H. Liu, S.T. Liu,  H. L. Hughes,  2006 IEEE SOI International Conference Proceedings, Pages 107-108
  9. S.T. Liu, H. Liu, N. Brewster, D. Nelson, K. Golke, G. Kirchner, H. Hughes, A. Campbell, J. Ziegler, "Limiting SEU Cross-sections of Deep Submicron SOI SRAMs”, , IEEE Trans. Nucl. Sci., Vol. 53, Issue 6, Part1, Dec. 2006, pages  3487-3493
  10. S. T. Liu, H. Liu, D. Nelson, H. Hughes, "Estimating Proton Induced SEU Cross-sections of SOI CMOS SRAMs”, Meet. Abstr.-Electrochem. Soc. 501, Page 541 (2006)
  11. S.T. Liu, H. Liu, E. Vogt, H. Hughes, P. McMarr, and A. Thompson, "Thermal Neutron Induced Upsets in SEU hardened SOI SRAMs”, presented at the 2006 Single Event Effects Symposium.
  12. H. Liu, D. Nelson, K. Golke, and S. Liu, "SEU Hardened 0.15m SOI SRAMs”,  presented at 2005 Hardened Electronics and Radiation Technology Conference.
  13. H. Liu, K. Golke, S. T. Liu, "A New Dose Rate Model for SOI MOSFETs and Its Implementation in SPICE”,   2005 IEEE SOI International Conference Proceedings, Pages 112-113
  14. D. Nelson, H. Liu, K. Golke, A. Kohli, "150nm SOI Embedded STRAMs with Very Low SER”,  2005 IEEE SOI International Conference Proceedings, Pages 188-190
  15. S. T. Liu, H. Liu, W. Heikkila, H. Hughes, A. Campbell, E. Petersen, P. McMarr, "Proton-induced Upset in SOI CMOS SRAMs”,  IEEE Trans. Nucl. Sci., Vol. 51, Issue 6, Part2, Dec. 2004, pages  3475-3479
  16. D. Fulkerson, and H. Liu, "A Charge-control SPICE Engineering Model for the Parasitic Bipolar Transistor Action in SOI CMOS Single-Event Upsets”, Feb., IEEE Trans. Nucl. Sci.,Vol. 51, Issue 1, part 2, Feb. 2004, pages 275-287
  17. S. T. Liu, H. Liu, "The SEU Performance  of an SOI 4M SRAM with Enriched  11B in BPSG”,  presented at the 2004 Hardened Electronics and Radiation Technology Conference
  18. S. T. Liu, H. Liu, "Neutron-Insensitive SOI CMOS 4M SRAMs”,  presented at 2004 Single Event Effects Symposium.
  19. H. Liu, S.T. Liu, K.W. Golke, D.K. Nelson, W.W. Heikkila, W.C. Jenkins, "Pronton Induced Single Event Upset in a 4M SOI SRAM”, 2003 IEEE SOI International Conference Proceedings, Pages 26-27
  20. H. Liu, et al., "Study of Crystal Precipitates on Borophosphosilicate Glass Films after Reflow”, presented at the 193rd ECS conference.
  21. R. Katti, A. Arrot, J. Drewes, W. Larson, H. Liu, Y. Lu,   T. Vogt, T. Zhu, "Submicron Pseudo-spin Valve Performance for Giant Magnetoresistive Random Access Memory Applications”,  Magnetics IEEE Trans., Vol. 37, Issue 4, Part 1, July 2001, Pages 1967-1969